Jet impingement boiling for chiplet semiconductors

The ever-increasing heat generation of 2.5D semiconductor packages used for AI and high-performance computing (HPC) demands energy-efficient cooling solutions with high heat transfer potential. In this study, we experimentally demonstrate two-phase direct liquid jet-impingement cooling on a 2.5D chiplet package thermal test vehicle (TTV) with a single logic chip and six HBMs. We further test two silicon backside micro pin-fin structuring methods: deep reactive ion etching and laser ablation. Experimental results show that the sub-microscale pores generated during laser ablation act as nucleation sites, allowing earlier boiling incipience at lower junction temperatures compared to both bare and DRIE-structured silicon surfaces. Additionally, two-phase dielectric fluids with different saturation temperatures (HFE-7000 and HFE-7100) were tested under identical operating conditions. HFE-7000 on the laser pin-fin surface demonstrated the highest junction-to-fluid heat transfer coefficient of 45.8 kW/m2K and lowest thermal resistance of 0.05 K/W. Meanwhile, the higher saturation temperature of HFE-7100 enabled stable boiling even at high TDPs reaching 1.2 kW at a 3 L/min flow rate. The findings highlight the coupled roles of jet-driven surface rewetting and backside surface structuring in enhancing critical heat flux for two-phase cooling of heterogeneously integrated 2.5D packages.